View HT162109_4533081.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HT1621 RAM Mapping 324 LCD Controller for I/O MCU
PATENTED
PAT No. : 099352
Technical Document
* Application Note
Features
* Operating voltage: 2.4V~5.2V * Built-in 256kHz RC oscillator * External 32.768kHz crystal or 256kHz frequency * Built-in 324 bit display RAM * 3-wire serial interface * Internal LCD driving frequency source * Software configuration feature * Data mode and command mode instructions * R/W address auto increment * Three data accessing modes * VLCD pin for adjusting LCD operating voltage * HT1621: 44-pin QFP package
source input
* Selection of 1/2 or 1/3 bias, and selection of 1/2 or
1/3 or 1/4 duty LCD applications
* Internal time base frequency sources * Two selectable buzzer frequencies (2kHz/4kHz) * Power down command reduces power consumption * Built-in time base generator and WDT * Time base or WDT overflow output * 8 kinds of time base/WDT clock sources * 324 LCD driver
HT1621B: 48-pin SSOP/LQFP packages HT1621D: 28-pin SKDIP package HT1621G: Gold bumped chip
General Description
The HT1621 is a 128 pattern (324), memory mapping, and multi-function LCD driver. The S/W configuration feature of the HT1621 makes it suitable for multiple LCD applications including LCD modules and display subsystems. Only three or four lines are required for the interface between the host controller and the HT1621. The HT1621 contains a power down command to reduce power consumption.
Selection Table
HT162X COM SEG Built-in Osc. Crystal Osc. HT1620 4 32 3/4 O HT1621 4 32 O O HT1622 8 32 O 3/4 HT16220 8 32 3/4 O HT1623 8 48 O O HT1625 8 64 O O HT1626 16 48 O O
Rev. 2.60
1
October 28, 2009
PATENTED
Block Diagram
D is p la y R A M
HT1621
OSCO OSCI CS RD WR DATA VDD VSS BZ BZ T o n e F re q u e n c y G e n e ra to r Con an T im C ir c tro l d in g u it
COM0 L C D D r iv e r / B ia s C ir c u it COM3 SEG0 SEG 31 VLCD W a tc h d o g T im e r and T im e B a s e G e n e r a to r IR Q
Note:
CS: Chip selection BZ, BZ: Tone outputs WR, RD, DATA: Serial interface COM0~COM3, SEG0~SEG31: LCD outputs IRQ: Time base or WDT overflow output
Pin Assignment
SEG1 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 0
44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 40 39 38 37 36 35 34
1
SEG SEG SEG SEG SEG SEG SEG SEG SGE SEG SEG 11 12 13 14 15 16 17 18 19 20 21
2
3
4
5
6
7
8
9
0
D SEG7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 CS RD WR DATA VSS OSCO OSCI VLCD VDD IR Q BZ BZ COM0 COM1 COM2 COM3 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SEG8 SEG9 SEG 10 SEG 11 SEG 12 C SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 SEG 18 SEG 19 SEG 20 SEG 21 SEG 22 SEG 23 SEG 24 SEG 25 SEG 26 SEG 27 SEG 28 SEG 29 SEG 30 SEG 31 C C V
CS RD WR ATA VSS LCD VDD BZ OM0 OM1 OM2
33 32 31 30
H T1621 4 4 Q F P -B
29 28 27 26 25 24 23
SE SE SE SE SE SE SE SE SE SE CO G2 G2 G2 G2 G2 G2 G2 G2 G3 G3 M3 1 SEG1 SEG1 SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 0
CS RD WR DATA VSS OSCO OSCI VLCD VDD IR Q BZ BZ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
0
SEG5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SEG3 SEG SEG SEG SEG SEG SEG SEG SGE SEG SEG SEG SEG 12 13 14 15 16 17 18 19 20 21 22 23 SEG1 CS RD WR DATA VSS VLCD VDD IR Q BZ COM0 COM1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SEG7 SEG9 SEG 11 SEG 13 SEG 15 SEG 17 SEG 19 SEG 21 SEG 23 SEG 25 SEG 27 SEG 29 SEG 31 COM2
9 1
H T1621B 4 8 L Q F P -A
8 2 SEG SEG SEG SEG SEG SEG SEG SEG COM COM COM COM 3 4 5 6 7 8 9 0 1
H T1621D 2 8 S K D IP -A
7
6
5
4
3
2
H T1621B 4 8 S S O P -A
31 3
30
24 25 26 28* 27* 29
N o te : * P le a s e n o te th a t in th e 4 8 - p in L Q F P p a c k a g e , th e S E G 2 7 a n d S E G 2 8 p in s a r e n o t in s e q u e n tia l o r d e r .
0
1
2
Rev. 2.60
2
October 28, 2009
PATENTED
Pad Assignment
SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG8 SEG9 SEG0 48 1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
HT1621
CS
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RD 2 3 4 5 6 WR DATA VSS OSCO
32 31 30 (0 ,0 ) 29 28 27 26 25 24
SEG 16 SEG 17 SEG 18 SEG 19 SEG 20 SEG 21 SEG 22 SEG 23 SEG 24 SEG 25 SEG 26 SEG 27 SEG 28
OSCI 7 VLCD VDD 9
IR Q
23 8 22 21 10 11 BZ 12
BZ
13 COM0
14 COM1
15 COM2
16 COM3
17 SEG 31
18 SEG 30
19 SEG 29
20
Chip size: 82 83 (mil)2 Bump height: 18mm 3mm Min. Bump spacing: 23.02mm Bump size: 76 76mm2 * The IC substrate should be connected to VDD in the PCB layout artwork.
Rev. 2.60
3
October 28, 2009
PATENTED
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 X -802.951 -927.055 -927.055 -927.055 -925.358 -925.358 -925.785 -925.785 -925.699 -896.840 -637.515 -452.726 -288.935 -189.915 -84.350 14.669 114.260 213.320 312.380 925.915 925.915 925.915 925.915 925.915 Y 939.295 343.250 244.230 89.374 -52.510 -151.360 -566.516 -675.287 -773.697 -939.537 -935.685 -935.685 -935.685 -935.685 -935.685 -935.685 -940.130 -940.130 -940.130 -867.615 -768.555 -669.495 -570.435 -437.375 Pad No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 X 925.915 925.915 925.915 925.915 925.915 925.915 925.915 925.915 849.589 750.530 651.469 552.409 453.349 354.289 255.230 156.169 57.109 -41.951 -141.010 -240.070 -339.130 -438.190 -537.250 -636.310
HT1621
Unit: mm Y -338.315 -239.255 -140.195 -41.134 57.925 156.986 256.046 355.106 939.295 939.295 939.295 939.295 939.295 939.295 939.295 939.295 939.295 939.295 939.295 939.295 939.295 939.295 939.295 939.295
Pad Description
Pad No. Pad Name I/O Function Chip selection input with pull-high resistor When the CS is logic high, the data and command read from or written to the HT1621 are disabled. The serial interface circuit is also reset. But if CS is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1621 are all enabled. READ clock input with pull-high resistor Data in the RAM of the HT1621 are clocked out on the falling edge of the RD signal. The clocked out data will appear on the DATA line. The host controller can use the next rising edge to latch the clocked out data. WRITE clock input with pull-high resistor Data on the DATA line are latched into the HT1621 on the rising edge of the WR signal. Serial data input/output with pull-high resistor Negative power supply, ground The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to generate a system clock. If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. But if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads can be left open. LCD power input Positive power supply Time base or WDT overflow flag, NMOS open drain output 2kHz or 4kHz tone frequency output pair LCD common outputs LCD segment outputs
1
CS
I
2
RD
I
3 4 5 7 6 8 9 10 11, 12 13~16 48~17
WR DATA VSS OSCI OSCO VLCD VDD IRQ BZ, BZ COM0~COM3 SEG0~SEG31
I I/O 3/4 I O I 3/4 O O O O
Rev. 2.60
4
October 28, 2009
PATENTED
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+5.5V Input Voltage..............................VSS-0.3V to VDD+0.3V
HT1621
Storage Temperature ............................-50oC to 125oC Operating Temperature...........................-40oC to 85oC
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD IDD1 Parameter Operating Voltage Operating Current 5V 3V IDD2 Operating Current 5V 3V IDD3 Operating Current 5V 3V ISTB Standby Current 5V 3V VIL Input Low Voltage 5V 3V VIH Input High Voltage 5V 3V IOL1 DATA, BZ, BZ, IRQ 5V 3V IOH1 DATA, BZ, BZ 5V 3V IOL2 LCD Common Sink Current 5V 3V IOH2 LCD Common Source Current 5V 3V IOL3 LCD Segment Sink Current 5V 3V IOH3 LCD Segment Source Current 5V 3V RPH Pull-high Resistor 5V DATA, WR, CS, RD 30 60 100 VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V DATA, WR, CS, RD 4.0 0.5 1.3 -0.4 -0.9 80 150 -80 -120 60 120 -40 -70 60 DATA, WR, CS, RD 0 2.4 No load, Power down mode Test Conditions VDD 3/4 3V Conditions 3/4 No load/LCD ON On-chip RC oscillator No load/LCD ON Crystal oscillator No load/LCD ON External clock source Min. 2.4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 Typ. 3/4 150 300 60 120 100 200 0.1 0.3 3/4 3/4 3/4 3/4 1.2 2.6 -0.8 -1.8 150 250 -120 -200 120 200 -70 -100 120 Max. 5.2 300 600 120 240 200 400 5 10 0.6 1.0 3.0 5.0 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 200
Ta=25C Unit V mA mA mA mA mA mA mA mA V V V V mA mA mA mA mA mA mA mA mA mA mA mA kW kW
Rev. 2.60
5
October 28, 2009
PATENTED
A.C. Characteristics
Symbol fSYS1 fSYS2 fSYS3 Parameter System Clock System Clock System Clock Test Conditions VDD Conditions Min. 192 3/4 3/4 3/4 3/4 3/4 3/4 4 Duty cycle 50% 5V 3V fCLK2 Serial Data Clock (RD pin) 5V fTONE tCS Tone Frequency (2kHz) 3V On-chip RC oscillator Tone Frequency (4kHz) Serial Interface Reset Pulse Width (Figure 3) 3/4 3V tCLK WR, RD Input Pulse Width (Figure 1) 5V Read mode tr, tf tsu th tsu1 th1 tOFF tSR Note: Rise/Fall Time Serial Data 3/4 Clock Width (Figure 1) Setup Time for DATA to WR, 3/4 RD Clock Width (Figure 2) Hold Time for DATA to WR, RD 3/4 Clock Width (Figure 2) Setup Time for CS to WR, RD 3/4 Clock Width (Figure 3) Hold Time for CS to WR, RD 3/4 Clock Width (Figure 3) VDD OFF Times (Figure 4) 3/4 3/4 3/4 3/4 3/4 3/4 VDD drop down to 0V 3/4 3.34 3/4 60 250 500 50 20 0.05 Read mode Write mode 6.67 1.67 CS Write mode 3.0 250 3.34 4.0 300 3/4 3/4 3/4 3/4 120 120 300 600 100 3/4 3/4 5.0 3/4 Duty cycle 50% 4 3/4 3/4 1.5 Typ. 256 32768 256 fSYS1/1024 fSYS2/128 fSYS3/1024 n/fLCD 3/4 3/4 3/4 3/4 2.0
HT1621
Ta=25C Max. 320 3/4 3/4 3/4 3/4 3/4 3/4 150 300 75 150 2.5 Unit kHz Hz kHz Hz Hz Hz s kHz kHz kHz kHz kHz kHz ns ms
3V On-chip RC oscillator 3/4 3/4 3/4 Crystal oscillator External clock source On-chip RC oscillator Crystal oscillator External clock source n: Number of COM
fLCD
LCD Clock
3/4 3/4
tCOM fCLK1
LCD Common Period Serial Data Clock (WR pin)
3/4 3V
125 3/4 125 3/4 160 3/4 3/4 3/4 3/4 3/4 3/4
ms ns ns ns ns ns ms V/ms
VDD Rising Slew Rate (Figure 4) 3/4
1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal Power-on Reset (POR) circuit will not operate normally. 2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for 20ms (min.) before rising to the normal operating voltage.
Rev. 2.50
6
May 13, 2009
PATENTED
tf W R,RD C lo c k 90% 50% 10% tr V tC
LK DD
HT1621
V a lid D a ta V th
U
DD
DB
50% tS
tC
GND
LK
GND V
DD
Figure 1
W R,RD C lo c k
50%
GND
Figure 2
tC
S
CS
50% tS
U1
V
DD
th
1
GND
V
DD
VDD
W R,RD C lo c k
50% F ir s t C lo c k L a s t C lo c k
0V
tS
R
GND
tO
FF
Figure 3
Figure 4 Power-on Reset Timing
Rev. 2.60
7
October 28, 2009
PATENTED
Functional Description
Display Memory - RAM The static display memory (RAM) is organized into 324 bits and stores the displayed data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the READ, WRITE, and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD pattern:
COM3 SEG0 SEG1 SEG2 SEG3 3 2 A d d r e s s 6 b its (A 5 , A 4 , ..., A 0 ) 1 COM2 COM1 COM0 0
HT1621
system power down command. But if the external clock source is chosen as the system clock, using the SYS DIS command can neither turn the oscillator off nor carry out the power down mode. The crystal oscillator option can be applied to connect an external frequency source of 32kHz to the OSCI pin. In this case, the system fails to enter the power down mode, similar to the case in the external 256kHz clock source operation. At the initial system power on, the HT1621 is at the SYS DIS state. Time Base and Watchdog Timer (WDT) The time base generator is comprised by an 8-stage count-up ripple counter and is designed to generate an accurate time base. The watch dog timer (WDT), on the other hand, is composed of an 8-stage time base generator along with a 2-stage count-up counter, and is designed to break the host controller or other subsystems from abnormal states such as unknown or unwanted jump, execution errors, etc. The WDT time-out will result in the setting of an internal WDT time-out flag. The outputs of the time base generator and of the WDT time-out flag can be connected to the IRQ output by a command option. There are totally eight frequency sources available for the time base generator and the WDT clock. The frequency is calculated by the following equation. 32kHz 2n where the value of n ranges from 0 to 7 by command options. The 32kHz in the above equation indicates that the source of the system frequency is derived from a crystal oscillator of 32.768kHz, an on-chip oscillator (256kHz), or an external frequency of 256kHz. fWDT = If an on-chip oscillator (256kHz) or an external 256kHz frequency is chosen as the source of the system frequency, the frequency source is by default prescaled to 32kHz by a 3-stage prescaler. Employing both the time base generator and the WDT related commands, one should be careful since the time base generator and WDT share the same 8-stage counter. For example, invoking the WDT DIS command disables the time base generator whereas executing the WDT EN command not only enables the time base generator but activates the WDT time-out flag output (connect the WDT
SEG 31 D3 D2 D1 D0
31 Addr D a ta
D a ta 4 b its (D 3 , D 2 , D 1 , D 0 )
RAM Mapping
System Oscillator The HT1621 system clock is used to generate the time base/Watchdog Timer (WDT) clock frequency, LCD driving clock, and tone frequency. The source of the clock may be from an on-chip RC oscillator (256kHz), a crystal oscillator (32.768kHz), or an external 256kHz clock by the S/W setting. The configuration of the system oscillator is as shown. After the SYS DIS command is executed, the system clock will stop and the LCD bias generator will turn off. That command is, however, available only for the on-chip RC oscillator or for the crystal oscillator. Once the system clock stops, the LCD display will become blank, and the time base/WDT lose its function as well. The LCD OFF command is used to turn the LCD bias generator off. After the LCD bias generator switches off by issuing the LCD OFF command, using the SYS DIS command reduces power consumption, serving as a
OSCI OSCO C r y s ta l O s c illa to r 32768H z E x te r n a l C lo c k S o u r c e 256kH z
S y s te m C lo c k 1 /8
O n - c h ip R C O s c illa to r 256kH z
System Oscillator Configuration Rev. 2.60 8 October 28, 2009
PATENTED
S y s te m C lo c k f= 3 2 k H z T im e r /W D T C lo c k S o u r c e s /2 n n=0~7
HT1621
/2 5 6
V W DT
DD
T IM E R
E N /D IS
W D T E N /D IS D CK R W DT Q IR Q E N /D IS
IR Q
/4
CLR
Timer and WDT Configurations time-out flag to the IRQ pin). After the TIMER EN command is transferred, the WDT is disconnected from the IRQ pin, and the output of the time base generator is connected to the IRQ pin. The WDT can be cleared by executing the CLR WDT command, and the contents of the time base generator is cleared by executing the CLR WDT or the CLR TIMER command. The CLR WDT or the CLR TIMER command should be executed prior to the WDT EN or the TIMER EN command respectively. Before executing the IRQ EN command the CLR WDT or CLR TIMER command should be executed first. The CLR TIMER command has to be executed before switching from the WDT mode to the time base mode. Once the WDT time-out occurs, the IRQ pin will stay at a logic low level until the CLR WDT or the IRQ DIS command is issued. After the IRQ output is disabled the IRQ pin will remain at the floating state. The IRQ output can be enabled or disabled by executing the IRQ EN or the IRQ DIS command, respectively. The IRQ EN makes the output of the time base generator or of the WDT time-out flag appear on the IRQ pin. The configuration of the time base generator along with the WDT are as shown. In the case of on-chip RC oscillator or crystal oscillator, the power down mode can reduce power consumption since the oscillator can be turned on or off by the corresponding system commands. At the power down mode the time base/WDT loses all its functions. On the other hand, if an external clock is selected as the source of system frequency the SYS DIS command turns out invalid and the power down mode fails to be carried out. That is, after the external clock source is selected, the HT1621 will continue working until system power fails or the external clock source is removed. After the system power on, the IRQ will be disabled. Tone Output A simple tone generator is implemented in the HT1621. The tone generator can output a pair of differential driving signals on the BZ and BZ, which are used to generate a single tone. By executing the TONE4K and TONE2K commands there are two tone frequency outputs selectable. The TONE4K and TONE2K commands set the tone frequency to 4kHz and 2kHz, respectively. The tone output can be turned on or off by invoking the TONE ON or the TONE OFF command. The tone outputs, namely BZ and BZ, are a pair of differential driving outputs used to drive a piezo buzzer. Once the system is disabled or the tone output is inhibited, the BZ and the BZ outputs will remain at low level. LCD Driver The HT1621 is a 128 (324) pattern LCD driver. It can be configured as 1/2 or 1/3 bias and 2 or 3 or 4 commons of LCD driver by the S/W configuration. This feature makes the HT1621 suitable for multiply LCD applications. The LCD driving clock is derived from the system clock. The value of the driving clock is always 256Hz even when it is at a 32.768kHz crystal oscillator frequency, an on-chip RC oscillator frequency, or an external frequency. The LCD corresponding commands are summarized in the table. The bold form of 1 0 0, namely 1 0 0, indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command, will be omitted. The LCD OFF command turns the LCD display off by disabling the LCD bias generator. The LCD ON command, on the other hand, turns the LCD display on by enabling the LCD bias generator. The BIAS and COM are the LCD panel related comFunction Turn off LCD outputs Turn on LCD outputs c=0: 1/2 bias option c=1: 1/3 bias option ab=00: 2 commons option ab=01: 3 commons option ab=10: 4 commons option
Name LCD OFF LCD ON
Command Code 10000000010X 10000000011X
BIAS & COM
1000010abXcX
Rev. 2.60
9
October 28, 2009
PATENTED
mands. Using the LCD related commands, the HT1621 can be compatible with most types of LCD panels. Command Format The HT1621 can be configured by the S/W setting. There are two mode commands to configure the HT1621 resources and to transfer the LCD display data. The configuration mode of the HT1621 is called command mode, and its command mode ID is 1 0 0. The command mode consists of a system configuration command, a system frequency selection command, a LCD configuration command, a tone frequency selection command, a timer/WDT setting command, and an operating command. The data mode, on the other hand, includes READ, WRITE, and READ-MODIFY-WRITE operations. The following are the data mode IDs and the command mode ID: Operation Read Write Read-Modify-Write Command Mode Data Data Data Command ID 110 101 101 100 Crystal Selection
HT1621
level pulse is required to initialize the serial interface of the HT1621. The DATA line is the serial data input/output line. Data to be read or written or commands to be written have to be passed through the DATA line. The RD line is the READ clock input. Data in the RAM are clocked out on the falling edge of the RD signal, and the clocked out data will then appear on the DATA line. It is recommended that the host controller read in correct data during the interval between the rising edge and the next falling edge of the RD signal. The WR line is the WRITE clock input. The data, address, and command on the DATA line are all clocked into the HT1621 on the rising edge of the WR signal. There is an optional IRQ line to be used as an interface between the host controller and the HT1621. The IRQ pin can be selected as a timer output or a WDT overflow flag output by the S/W setting. The host controller can perform the time base or the WDT function by being connected with the IRQ pin of the HT1621.
The mode command should be issued before the data or command is transferred. If successive commands have been issued, the command mode ID, namely 1 0 0, can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to 1 and the previous operation mode will be reset also. Once the CS pin returns to 0 a new operation mode ID should be issued first. Interfacing Only four lines are required to interface with the HT1621. The CS line is used to initialize the serial interface circuit and to terminate the communication between the host controller and the HT1621. If the CS pin is set to 1, the data and command issued between the host controller and the HT1621 are first disabled and then initialized. Before issuing a mode command or mode switching, a high
A 32768Hz crystal can be directly connected to the HT1621 via OSCI and OSCO. In order to obtain the correct frequency, two additional load capacities (C1, C2) are needed. The value of the capacity depends on how accurate the crystal is. We suggest that you can follow the table, which suggests the value of capacities.The table illustrations the suggestion value of capacities (C1, C2)
32768H z OSCI C1 C2 OSCO
Crystal Error 10ppm 10~20ppm
Capacity Value 0~10p 10~20p
Timing Diagrams
READ Mode (Command Code : 1 1 0)
CS
WR
RD 1 1 0 A5 A4 A3 A2 A1 A0 D0D1 D2 D3 M e m o ry A d d re s s 1 (M A 1 ) D a ta (M A 1 ) 1 1
10
DATA
0
A5 A4 A3 A2 A1 A0 D0D1 D2 D3 M e m o ry A d d re s s 2 (M A 2 ) D a ta (M A 2 )
October 28, 2009
Rev. 2.60
PATENTED
READ Mode (Successive Address Reading)
HT1621
CS
WR
RD 1 1 0 A5 A4 A3 A2 A1 A0 D0D1 D2 D3 D0D1 D2 D3 D0D1 D2 D3 D0D1 D2 D3 D0 D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 ) M e m o ry A d d re s s (M A ) D a ta (M A )
DATA
WRITE Mode (Command Code : 1 0 1)
CS
WR 1 0 1 A5 A4 A3 A2 A1 A0 D0D1 D2 D3 M e m o ry A d d re s s 1 (M A 1 ) D a ta (M A 1 ) 1 0 1 A5 A4 A3 A2 A1 A0 D0D1 D2 D3 M e m o ry A d d re s s 2 (M A 2 ) D a ta (M A 2 )
DATA
WRITE Mode (Successive Address Writing)
CS
WR 1 0 1 A5 A4 A3 A2 A1 A0 D0D1 D2 D3 D0D1 D2 D3 D0D1 D2 D3 D0D1 D2 D3 D0 D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 ) M e m o ry A d d re s s (M A ) D a ta (M A )
DATA
Read-Modify-Write Mode (Command Code : 1 0 1)
CS
WR
RD 1 0 1 A5 A4 A3 A2 A1 A0 D0D1 D2 D3 D0D1 D2 D3 M e m o ry A d d re s s 1 (M A 1 ) D a ta (M A 1 ) D a ta (M A 1 ) 1 0 1 A5 A4 A3 A2 A1 A0 D0D1 D2 D3 M e m o ry A d d re s s 2 (M A 2 ) D a ta (M A 2 )
DATA
Rev. 2.60
11
October 28, 2009
PATENTED
Read-Modify-Write Mode (Successive Address Accessing)
CS
HT1621
WR
RD 1 0 1 A5 A4 A3 A2 A1 A0 D0D1 D2 D3 D0D1 D2 D3 D0D1 D2 D3 D0D1 D2 D3 D0D1 D2 D3 D0 M e m o ry A d d re s s (M A ) D a ta (M A ) D a ta (M A ) D a ta (M A + 1 ) D a ta (M A + 1 ) D a ta (M A + 2 )
DATA
Command Mode (Command Code : 1 0 0)
CS
WR 1 0 0 C8C7C6C5C4 C3C2C1C0 C8C7C6C5C4 C3C2C1C0 Com m and 1 C o m m a n d ... Com m and i
DATA
Com m and or D a ta M o d e
Mode (Data and Command Mode)
CS
WR
DATA
Com m and or D a ta M o d e
A d d re s s & D a ta
Com m and or D a ta M o d e
A d d re s s a n d D a ta
Com m and or D a ta M o d e
A d d re s s a n d D a ta
RD
Note:
It is recommended that the host controller should read in the data from the DATA line between the rising edge of the RD line and the falling edge of the next RD line.
Rev. 2.60
12
October 28, 2009
PATENTED
Application Circuits
Host Controller with an HT1621 Display System
HT1621
*
MCU
* R
CS RD WR DATA
VDD * VLCD
VR
H T1621B
BZ P ie z o BZ
C lo c k O u t E x te r n a l C o lc k 1 E x te r n a l C o lc k 2 O n - c h ip O S C C ry s ta l 32768H z C1 C2
IR Q OSCI OSCO COM0~COM3 SEG 0~SEG 31
1 /2 o r 1 /3 B ia s ; 1 /2 , 1 /3 o r 1 /4 D u ty
LCD
Panel
Note:
The connection of IRQ and RD pin can be selected depending on the requirement of the MCU. The voltage applied to VLCD pin must be lower than VDD. Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kW20%. Adjust R (external pull-high resistance) to fit users time base clock. In order to obtain the correct frequency, two additional load capacities (C1, C2) are needed. The value of the capacity depends on how accurate the crystal is. We suggest that you can follow the table, which suggests the value of capacities. The table illustrations the suggestion value of capacities (C1,C2) Crystal Error 10ppm 10~20ppm Capacity Value 0~10p 10~20p
Command Summary
Name READ WRITE READ-MODIFYWRITE SYS DIS SYS EN LCD OFF LCD ON TIMER DIS WDT DIS TIMER EN WDT EN Rev. 2.60 ID 110 101 101 100 100 100 100 100 100 100 100 Command Code A5A4A3A2A1A0D0D1D2D3 A5A4A3A2A1A0D0D1D2D3 A5A4A3A2A1A0D0D1D2D3 0000-0000-X 0000-0001-X 0000-0010-X 0000-0011-X 0000-0100-X 0000-0101-X 0000-0110-X 0000-0111-X 13 D/C D D D C C C C C C C C Function Read data from the RAM Write data to the RAM READ and WRITE to the RAM Turn off both system oscillator and LCD Yes bias generator Turn on system oscillator Turn off LCD bias generator Turn on LCD bias generator Disable time base output Disable WDT time-out flag output Enable time base output Enable WDT time-out flag output October 28, 2009 Yes Def.
PATENTED
Name TONE OFF TONE ON CLR TIMER CLR WDT XTAL 32K RC 256K EXT 256K ID 100 100 100 100 100 100 100 Command Code 0000-1000-X 0000-1001-X 0000-11XX-X 0000-111X-X 0001-01XX-X 0001-10XX-X 0001-11XX-X D/C C C C C C C C Function Turn off tone outputs Turn on tone outputs
HT1621
Def. Yes
Clear the contents of time base generator Clear the contents of WDT stage System clock source, crystal oscillator System clock source, on-chip RC oscillator System clock source, external clock source LCD 1/2 bias option ab=00: 2 commons option ab=01: 3 commons option ab=10: 4 commons option LCD 1/3 bias option ab=00: 2 commons option ab=01: 3 commons option ab=10: 4 commons option Tone frequency, 4kHz Tone frequency, 2kHz Disable IRQ output Enable IRQ output Time base/WDT clock output:1Hz The WDT time-out flag after: 4s Time base/WDT clock output:2Hz The WDT time-out flag after: 2s Time base/WDT clock output:4Hz The WDT time-out flag after: 1s Time base/WDT clock output:8Hz The WDT time-out flag after: 1/2s Time base/WDT clock output:16Hz The WDT time-out flag after: 1/4s Time base/WDT clock output:32Hz The WDT time-out flag after: 1/8s Time base/WDT clock output:64Hz The WDT time-out flag after: 1/16s Time base/WDT clock output:128Hz The WDT time-out flag after: 1/32s Test mode, user dont use. Normal mode Yes Yes Yes Yes
BIAS 1/2
100
0010-abX0-X
C
BIAS 1/3
100
0010-abX1-X
C
TONE 4K TONE 2K IRQ DIS IRQ EN F1 F2 F4 F8 F16 F32 F64 F128 TEST NORMAL Note:
100 100 100 100 100 100 100 100 100 100 100 100 100 100
010X-XXXX-X 011X-XXXX-X 100X-0XXX-X 100X-1XXX-X 101X-X000-X 101X-X001-X 101X-X010-X 101X-X011-X 101X-X100-X 101X-X101-X 101X-X110-X 101X-X111-X 1110-0000-X 1110-0011-X
C C C C C C C C C C C C C C
X : Don,t care A5~A0 : RAM addresses D3~D0 : RAM data D/C : Data/command mode Def. : Power on reset default All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base/WDT clock frequency can be derived from an on-chip 256kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 256kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1621 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the HT1621.
Rev. 2.60
14
October 28, 2009
PATENTED
Package Information
28-pin SKDIP (300mil) Outline Dimensions
HT1621
A
28 15 14 1
B
H C D E F G I
Symbol A B C D E F G H I
Dimensions in mil Min. 1375 278 125 125 16 50 3/4 295 3/4 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 Max. 1395 298 135 145 20 70 3/4 315 375
Rev. 2.60
15
October 28, 2009
PATENTED
44-pin QFP (10mm10mm) Outline Dimensions
C D G 23 I 34 22 L F A B E 44 12 K 1 11 a J 33 H
HT1621
Symbol A B C D E F G H I J K L a
Dimensions in mm Min. 13.00 9.90 13.00 9.90 3/4 3/4 1.90 3/4 0.25 0.73 0.10 3/4 0 Nom. 3/4 3/4 3/4 3/4 0.80 0.30 3/4 3/4 3/4 3/4 3/4 0.10 3/4 Max. 13.40 10.10 13.40 10.10 3/4 3/4 2.20 2.70 0.50 0.93 0.20 3/4 7
Rev. 2.60
16
October 28, 2009
PATENTED
48-pin SSOP (300mil) Outline Dimensions
HT1621
48 A
25 B
1 C C'
24
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 395 291 8 613 85 3/4 4 25 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 420 299 12 637 99 3/4 10 35 12 8
Rev. 2.60
17
October 28, 2009
PATENTED
48-pin LQFP (7mm7mm) Outline Dimensions
HT1621
C D 36 25 G H
I 37 24
F A B E 48 13 K 1 12 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 8.90 6.90 8.90 6.90 3/4 3/4 1.35 3/4 3/4 0.45 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.50 0.20 3/4 3/4 0.10 3/4 3/4 3/4 Max. 9.10 7.10 9.10 7.10 3/4 3/4 1.45 1.60 3/4 0.75 0.20 7
Rev. 2.60
18
October 28, 2009
PATENTED
Product Tape and Reel Specifications
Reel Dimensions
T2 D
HT1621
A
B
C
T1
SSOP 48W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.00.1 13.0+0.5/-0.2 2.00.5 32.8+0.3/-0.2 38.20.2
Rev. 2.60
19
October 28, 2009
PATENTED
Carrier Tape Dimensions
D
E F W C B0
HT1621
P0
P1
t
D1
P K2 A0
K1
R e e l H o le ( C ir c le ) p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e . R e e l H o le ( E llip s e ) IC
SSOP 48W Symbol W P E F D D1 P0 P1 A0 B0 K1 K2 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 32.00.3 16.00.1 1.750.1 14.20.1 1.5+0.1/-0.0 1.50+0.25/-0.00 4.00.1 2.00.1 12.00.1 16.200.1 2.40.1 3.20.1 0.350.05 25.50.1
Rev. 2.60
20
October 28, 2009
PATENTED
HT1621
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2009 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 2.60
21
October 28, 2009

▲Up To Search▲

Price & Availability of HT162109

	To Download HT162109 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .